Wide band gap bipolar transistor with reduced thermal runaway

ABSTRACT

A bipolar transistor with vertical geometry comprises a base region ( 1 ) provided with a base contact ( 21 ), emitter and collector regions ( 2,3 ) arranged to extract minority carriers from the base region, and an excluding structure for counteracting entry of minority carriers into the base region via the base contact, wherein the base region has a bandgap of greater than 0.5 eV and a doping level greater than 10 17  cm −3 . As shown the base includes an excluding heterojunction ( 4 ) preventing entry of carriers from the base contact ( 21 ), but alternatively the base region could comprise a “high-low” doping homojunction. The construction shows improved resistance to thermal runaway even in multi-finger transistors. It is particularly useful for high power, high frequency transistors, e.g. base on gallium indium arsenide. The collector region preferably has a heterostructure.

The present invention relates to bipolar transistors of the kind whichimplement exclusion and extraction of minority carriers from the base,and in particular to transistors in which the base region has a widebandgap, i.e. a wide energy gap between the valence band and conductionband.

The difference in bandgap between the emitter and base regions of abipolar transistor has a critical effect on current gain, and indetermining ƒ_(T) (ƒ_(T) is the highest frequency at which h_(fe) isabove one). A main method of tailoring a band gap difference is to varythe semiconductor composition on one or both sides of a heterojunction.

Gallium indium arsenide (GaInAs) materials are particularly useful inthat they have been demonstrated to provide the highest ƒ_(T) of anybipolar transistor. This type of device has been disclosed for examplein EP 0 977 250 (Daimler Chrysler AG). However, while developments insuch devices have concentrated on improving performance, e.g. ƒ_(T) andh_(fe), they have largely failed to deal with the practical limitationsof high frequency use. High frequency operation, as required inmicrowave and radio communications, results in high levels of heatgeneration and in practice thermal runaway effects can be the limitingfactor in operation.

As is well known, thermal runaway can occur in bipolar devices when anemitter contact is forward biased. For instance, under constantbase-emitter voltage conditions when the current through the devicerises, the temperature also rises, reducing the base-emitter turn-onvoltage and so enabling the current to rise even further. This type ofpositive feedback process can lead to damage in the device unless thecurrent is limited in some manner.

For example, in a multi-finger device, this thermal effect can cause onefinger in the device to have a lower turn-on voltage than the others sothat substantially all of the collector current flows through the onefinger. The gain of the device may be severely affected, andirreversible damage can arise if the condition is allowed to persist.The problem occurs even at constant base current operation.

A related problem is that hot spots can arise even within one finger,which can similarly cause collapse in the gain and/or burnout. Thiseffect generally occurs only at constant base voltage operation.However, it is increasingly a problem in modern devices with lowparasitic base and emitter resistances, where ballasting effects, thatis where series resistance damps out instability (see, for example, Liouet al., IEEE Int. Microwave Symp. Dig., 281 (1993)), are absent orgreatly reduced.

The foregoing considerations are particularly relevant for example tomobile communications devices such as telephones, where high power, highfrequency signal amplification is required for radio frequency signaltransmission.

Various means of mitigating this problem have been proposed, for exampleby ensuring that the heat in the device is spread uniformly over thedevice (see, for example, Bayraktaroglu et al., IEEE Electron DeviceLetters, 14, 493 (1993)), which however has only a limited effect. Aproposal intentionally to incorporate base or collector ballastresistors has the undesirable effect of reducing the gain. The presentinvention seeks to overcome such limitations.

The present invention provides a bipolar transistor with a verticalgeometry having a base region provided with a base contact, emitter andcollector regions arranged to extract minority carriers from the baseregion, and a structure for counteracting entry of minority carriersinto the base region via the base contact, wherein the base region has abandgap of greater than 0.5 eV and a doping level greater than 10¹⁷cm⁻³.

In a transistor with a vertical geometry the separation between theemitter and collector is defined by the growth of the material, and socan be determined to monolayer thickness using molecular beam epitaxy.The transistor of the embodiment has emitter and collector regions onopposed sides of a base layer, and the thinness of the base layer, interalia, enables high frequency operation, but at the risk of thermalrunaway. By contrast, the emitter-collector separation in transistorswith a horizontal (or lateral) geometry is determined by lithography.The consequential much greater characteristic length provides much lessinteraction between emitter and collector and hence a reduced gain, andreduced speed. Characteristically the emitter and collector regions arespaced laterally on the same side of the base region, as in Fujitsudiscussed below.

An example of a transistor with horizontal geometry is disclosed in JP050114602 (Fujitsu). Here a heterostructure base is provided to improvecurrent gain, although it is believed that in practice it will have verylittle effect. Because it will be a low gain device, the problem ofthermal runaway would not be expected to arise and it is not addressedin this patent. The only identifiable material is silicon, with an SiCor “compound semiconductor” wide gap layer.

For brevity in the description, the structure for counteracting entry ofminority carriers into the base via the base contact will henceforthalternatively be termed an excluding structure. An excluding structureacts to accept majority carriers but does not supply minority carriers.

In a transistor according to the invention the excluding structure maybe an excluding heterostructure or heterojunction, with a barrier toprevent carriers entering the base region. A heterostructure comprisesmaterials with different band gaps on either side of the junction, forexample in the present case a p⁺p⁺ junction, where the underscoreindicates a wider band gap than that of the corresponding p layer.

Alternatively, the excluding structure may be an implanted region withinthe base region, providing a “high-low” differentially dopedhomojunction (semiconductor material with the same bandgap either sideof the junction where a dopant concentration alters from one side of thejunction to the other) which inhibits minority carrier entry into thebase region. Such a structure may be for example a p⁺⁺p⁺ junction (the ⁺or ⁺⁺ refer to overdoping and increased overdoping compared to the samelayer type, and conversely ⁻ and ⁻ refer to underdoping) which compriseadjacent layers of the same semiconductor material but with differentdoping or carrier levels. Theoretically at least it would be possible touse different materials with the same bandgap either side of thejunction, and with different carrier levels, so that this constructionis more generally described as a ‘high-low’ doping junction. However,there are usually difficulties in matching the lattice constants ofdifferent materials.

The homojunction alternative not only permits simpler fabrication, butalso allows the use of a wide gap passivation layer between the base andemitter regions, if desired. Such a passivation layer can improveperformance by reducing recombination in the base region, whichotherwise causes increased leakage and reduced current gain.

The transistor may be a high power III-V heterostructure bipolartransistor, preferably a high frequency transistor, for example ofindium phosphide and gallium indium arsenide. One particularly suitableform is a transistor laid out in a multi-finger array, i.e. the body ofthe device is cut into fingers to facilitate heat removal from everypart, and the base and emitter contacts are interdigitated so thatcurrent may be input and output more easily.

Particularly where the transistor is based on III-V materials, but notlimited to transistors of that type, the emitter may be aheterostructure. No such emitter is disclosed in Fujitsu mentionedabove.

In devices according to the invention thermal runaway is reduced, andthey may therefore be operated at higher temperature or higher current.The stability of multi-finger devices may be increased without, forexample, resorting to ballast resistors.

Our copending GB Application No 0012925.4 describes and claims a bipolartransistor having emitter and collector regions arranged to extractminority carriers from the base region, a structure for counteractingentry of minority carriers into the base region via the base contact (anexcluding structure), the base region having a band gap of less than 0.5eV and a doping level greater than 10¹⁷ cm⁻³. Thus the use of aconstruction of this type is already known, but in respect of low bandgap materials only. However, this arrangement has now surprisingly beenfound to have the unexpected benefit of reducing thermal runaway inwider band-gap material bipolar transistors, where intrinsic conductionis not important under normal conditions.

Semiconductor materials suitable for use in the invention have a bandgap of greater than 0.5 eV, possibly greater than 0.52 eV, or even 0.55eV or more. While any suitable such material known in the art may beemployed, some preferred semi-conductor materials are GaAs, indiumgallium arsenide (InGaAs), InGaAsSb, GaN, indium phosphide (InP), InGaP,AlGaN, AlGaAs, and InAlAs. In particular GaAs, InGaAs, InGaAsSb and GaNare useful materials for the base region, and in an excludingheterostructure InP, InGaP, AlGaN, AlGaAs and InAlAs are useful wide gapmaterials.

Transistors according to the invention preferably comprise more than onesemiconductor composition with different bandgaps, so providing aheterostructure or heterojunction device. The heterostructure may occurin the base or collector region, for example.

Adjacent regions with different bandgaps may also have different dopantlevels, for example a heterojunction p⁺⁺p⁺.

In a preferred from of transistor according to the invention, thecollector region includes a heterostructure. This construction has beenfound to decrease thermal runaway to an unexpected extent.

Transistors according to the invention may be fabricated using methodsknown to the person skilled in the art. Preferably, an excludingstructure is formed by using regrowth to grow a p⁺p⁺ heterostructure, orby implanting p type dopants to produce a p⁺⁺p⁺ homostructure.

Transistors according to the invention may alternatively be fabricatedby leaving the wide bandgap emitter material in place over the extrinsicbase after the emitter mesa is etched instead of etching down to the topof the base. The wide bandgap material would then just be etched awayunder the base contact (to improve contact resistance), and/or the basecontact implant used to type convert it to p-type. The wide bandgapregion then provides a passivation layer on top of the extrinsic base,which reduces recombination currents in the base, improving currentgain.

While examples of junctions provided in this application relate to NPNbipolar transistors, it should be understood that similar considerationsapply for PNP bipolar transistors.

The invention extends to a method of reducing the tendency to thermalrunaway in a bipolar transistor with a vertical geometry having a baseregion provided with a base contact, emitter and collector regionsarranged to extract minority carriers from the base region, the baseregion having a bandgap of greater than 0.5 eV and a doping levelgreater than 10¹⁷ cm⁻³, by providing a structure for counteracting entryof minority carriers into the base region via the base contact.

Further features and advantages of the invention will become clear uponconsideration of the appended claims, to which the reader is referred,and upon a reading of the following more detailed description ofexemplary embodiments of the invention, made with reference to theaccompanying drawings, in which:

FIG. 1 is a schematic cross-sectional view of a transistor of theinvention with an excluding heterostructure;

FIG. 2 is a schematic cross-sectional view of a transistor of theinvention with an excluding homostructure;

FIG. 3 is a graph showing a Gummel plot for the transistor of FIG. 1 andfor an equivalent device without the excluding heterostructure;

FIG. 4 shows the thermal characteristics of the transistor of FIG. 1 and

FIG. 5 shows the thermal characteristics of the device of the equivalentdevice to that of FIG. 1 without the excluding heterostructure.

FIG. 1 shows a schematic cross-sectional view of an NPN bipolartransistor comprising a base 1, an emitter 2 and a relatively largecollector 3. The excluding structure comprises a p⁺p⁺ junctionheterojunction 4. The figures in brackets used in relation to thisFigure and in FIG. 2 refer to carrier concentrations.

A 0.3 μm thick sub-collector layer 12 of n InGaAs (6×10¹⁸) and a 0.6 μmcollector layer 13 of n InGaAs (1×10¹⁶) successively overlie a substratelayer 11 of semi-insulating InP. A 70 nm thick base layer 14 of p InGaAs(1×10¹⁹) lies over layer 13 and different areas thereof are in turnoverlaid by a 100 nm thick emitter layer 15 of n InP (4×10¹⁷) and a 100nm thick excluding base contact layer 19 of p InP (2×10¹⁹). Layer 15 isoverlaid in turn by a 100 nm thick emitter cap layer 16 of n InP(2×10¹⁸), a 150 nm thick emitter contact layer 17 of n InGaAs (1×10¹⁹)and a emitter metal contact layer 18. Layer 19 is overlaid in turn by a100 nm thick base cap/contact layer 20 of p InGaAs (2×10¹⁹), and a basemetal contact layer 21.

A metal contact layer 22 is provided on sub-collector layer 12.

A comparative device used in the comparisons below is constructed as inFIG. 1 above but with the base cap/contact layer 20 and the base contactlayer 19 omitted.

FIG. 2 shows a schematic cross-sectional view of an NPN bipolartransistor comprising a base 1, an emitter 2 and a relatively largecollector 3. The excluding structure comprises a p⁺p⁺ homojunction 5.

A 0.3 μm thick sub-collector layer 32 of n InGaAs (6×10¹⁸) and a 0.6 μmcollector layer 33 of n InGaAs (1×10¹⁶) successively overlie a substratelayer 31 of semi-insulating InP. A 70 nm thick base layer 34 of p InGaAs(1×10¹⁹) lies over layer 33 but includes a local 100 nm thick region ofp InP (2×10¹⁹) providing a base excluding contact 40 which carries ametal base cap layer 41. Layer 34 is in turn overlaid by a 100 nm thickemitter layer 35 of n InP (4×10¹⁷), a 100 nm thick emitter cap layer 36of n InP (2×10¹⁸), a 150 nm thick emitter contact layer 37 of n InGaAs(1×10¹⁹) and a metal emitter contact layer 38.

A metal contact layer 42 is provided on sub-collector layer 12.

FIG. 3 illustrates thermal runaway characteristics of the device of FIG.1 and the comparative device mentioned above, as obtained by 2Dthermal/drift-diffusion modelling. It is a Gummel plot of collector andbase currents (in amps per micron—2d simulation) versus base voltage atV_(ce)=0.8 V. The upper part 51 of the plot shows the collector currentand the lower part 52 the base current, and it will be seen that thedevice of the invention, with the excluding structure, permits largervalues of current before the onset of thermal runaway. The devicewithout the excluding contact shows marked thermal runaway as shown bythe continued rise in the both base and collector currents at V_(be)˜0.9V (when the devices are modelled, the current-voltage curves actuallyhave an infinitely steep slope at this point, and it should be notedthat the vertical axis is in any case exponential). In contrast, thedevice of the invention remains stable out to at least 1.5 V asindicated by the portions 55, 56.

The addition of the base contact greatly reduces the temperaturecoefficient of the base-emitter junction, allowing stable operation overthe whole range of base-emitter voltages. The decreased base currentnecessary for a given collector current also means that the current gainis increased by about 10% in normal operation.

FIGS. 4 and 5 are contour plots respectively showing the temperaturecharacteristics of the FIG. 1 transistor and the comparative device at abase-emitter voltage V_(be) of 0.9V. The temperature of the countersincreases in the direction of the arrows A and B respectively. In FIG. 4the lowest temperature region 60 shown is at about 330° C. and thehighest temperature region 62 shown is at about 375° C. In FIG. 5 thelowest temperature region 61 shown is at about 325° C. and the highesttemperature region 62 shown is at about 335° C. Thus lower temperatureoperation of the transistor of FIG. 5 according to the invention isclearly illustrated. It is clear that the comparative device reachesvery high temperatures, increasing the chance of device failure andgreatly reducing device lifetime.

1. A bipolar transistor with a vertical geometry having a base regionhaving two sides and provided with a base contact, emitter and collectorregions arranged to extract minority carriers from the base region, anda structure for counteracting entry of minority carriers into the baseregion via the base contact, wherein the base contact and emitter regionare upstanding from the same side of the base region and the base regionhas a bandgap greater than 0.5 eV and a doping level greater than 10¹⁷cm⁻³.
 2. A transistor according to claim 1 wherein the structure forcounteracting entry of minority carriers comprises a heterostructure. 3.A transistor according to claim 1 based on III-V materials.
 4. Atransistor according to claim 1 wherein the base region comprises one ofGaAs, InGaAs, InGaAsSb and GaN.
 5. A transistor according to claim 1wherein the structure for counteracting entry comprises one of InP,InGaP, AlGaN, AlGaAs and InAlAs.
 6. A transistor according to claim 1wherein the transistor is a heterostructure.
 7. A transistor accordingto claim 1 wherein the transistor is a high frequency transistor.
 8. Atransistor according to claim 1 wherein the transistor is ofmulti-finger array construction.
 9. A transistor according to claim 1wherein the bandgap is greater than 0.52 eV.
 10. A method of reducing atendency to thermal runaway in a vertical geometry bipolar transistorhaving a base region provided with a base contact and emitter andcollector regions arranged to extract minority carriers from the baseregion, the base contact and the emitter region being upstanding fromthe same side of the base region and the base region having a bandgap ofgreater than 0.5 eV and a doping level greater than 10¹⁷ cm⁻³, and themethod incorporating providing a structure for counteracting entry ofminority carriers into the base region via the base contact.
 11. Abipolar transistor with a vertical geometry having a base regionprovided with a base contact, emitter and collector regions arranged toextract minority carriers from the base region, and a homostructure withdifferential doping for counteracting entry of minority carriers intothe base region via the base contact, wherein the base region has a bandgap greater than 0.5 eV and a doping level greater than 10¹⁷ cm⁻³.
 12. Atransistor according to claim 11 wherein the heterostructure collectorregion comprises a wide gap material which is one of InP, InGaP, AlGaN,AlGaAs and InAlAs.
 13. A bipolar transistor with a vertical geometryhaving a base region provided with a base contact, emitter and collectorregions arranged to extract minority carriers from the base region, anda structure for counteracting entry of minority carriers into the baseregion via the base contact, wherein the emitter region is aheterostructure and the base region has a band gap greater than 0.5 eVand a doping level greater than 10¹⁷ cm⁻³.
 14. A transistor according toclaim 13 wherein the heterostructure emitter region comprises a wide gapmaterial selected from InP, InGaP, AIGaN, AIGaAs and InAlAs.
 15. Abipolar transistor with a vertical geometry having a base regionprovided with a base contact, emitter and collector regions arranged toextract minority carriers from the base region, and a structure forcounteracting entry of minority carriers into the base region via thebase contact, wherein the collector region is a heterostructure and thebase region has a band gap greater than 0.5 eV and a doping levelgreater than 10¹⁷ cm⁻³.
 16. A bipolar transistor with a verticalgeometry having a base region provided with a base contact, emitter andcollector regions arranged to extract minority carriers from the baseregion, and a structure for counteracting entry of minority carriersinto the base region via the base contact, wherein the collector regionis a heterostructure incorporating a wide gap material which is one ofInP, InGaP, AlGaN, AlGaAs and InAlAs and the base region has a band gapgreater than 0.5 eV and a doping level greater than 10¹⁷ cm⁻³.
 17. Abipolar transistor with a vertical geometry having a base regionprovided with a base contact, emitter and collector regions arranged toextract minority carriers from the base region, and a structure forcounteracting entry of minority carriers into the base region via thebase contact, wherein the emitter region is a heterostructureincorporating a wide gap material which is one of InP, InGaP, AlGaN,AlGaAs and InAlAs and the base region has a band gap greater than 0.5 eVand a doping level greater than 10¹⁷ cm⁻³.